The present invention relates to a delay computation apparatus and delay computation method for a logic circuit, and a storage medium that stores a delay computation program. More particularly, the invention relates to a delay computation apparatus, delay computation method and a storage medium that stores a delay computation program for determining a path of a logic circuit with maximum or minimum delay times.
A conventional delay computation apparatus or method of this type collectively traces, by a depth first search (hereinafter referred to as a CFS), each of a plurality of logic paths beginning with a single starting point. More specifically, the conventional apparatus or method computes a critical path by using the delay times of elements and wiring included in a logic circuit, and by collectively tracing all end points of a plurality of logic paths as a trace object. However, in this conventional delay computation apparatus or method, a true critical path is not necessarily obtained because there are factors which make the conventional apparatus or method unable to compute the actual delay times of logic paths. Such factors include, for example, clock skew.
An example of the conventional delay computation apparatus is described in Japanese Patent Application Laid-Open No. 5-189511. In a logic circuit consisting of mutually different logic devices, e.g., where the sender flip-flop (FF) and the receiver FF in the logic path differ in logic, the conventional apparatus described in the aforementioned publication computes delay time by referring to a clock skew value in a clock skew value table which is based on a combination of these different logic devices.
While this conventional delay computation apparatus can compute a critical path based on the clock skew between different logic circuits, the conventional apparatus cannot compute a critical path when the clock skews between registers differ within the same logic.
For instance, in a logic path including a first register and a second register, if a delay time of a path leading from the first register to the second register is merely computed, the true delay time will not be necessarily computed. This is because when clock skew has occurred between a clock signal supplied to the first register and a clock signal supplied to the second register, the true delay time will change because of the clock skew. In most cases, if there are a plurality of registers, clock skew between registers will occur because the clock paths for supplying clock signals to the registers also differ from each other.
Accordingly, an object of the present invention is to provide a delay computation apparatus which accurately computes the critical path of a plurality of logic paths.
Another object of the present invention is to provde a delay computation apparatus which computes the true delay time of a logic path when clock skew occurs between registers included in the logic path.
According to one aspect of the present invention, an apparatus for computing delay times of logic paths included in a logic circuit, which has a plurality of elements whose output is determined by the input of a clock signal and at least one signal which is not the clock signal, is provided which comprises: a first element which stores information about the logic circuit; a second element which groups pairs of elements into groups based on the clock skew value of the pairs of the elements, wherein each group has a specific range of clock skew values; and a third element which computes a delay time for each of the pairs of elements grouped by the second element by using a predetermined clock skew value, which is within the range used in the second element, and the information about the logic circuit stored in the first element.
According to another aspect of the present invention, an apparatus for computing delay times of logic paths included in a logic circuit which has a plurality of elements whose output is determined by the input of a clock signal and at least one signal which is not the clock signal, is provided which comprises: first storage means for storing information about the logic circuit; means for grouping the pairs of the elements into groups based on the clock skew value of the pairs of the elements, wherein each group has a specific range of clock skew values; and means for computing the delay time for each of the pairs of the elements grouped by the grouping means by using the predetermined clock skew value, which is within the range used in the grouping means, and the information about the logic circuit stored in the first storage means.
According to another aspect of the present invention, a method for computing delay times of logic paths included in a logic circuit which has a plurality of elements whose output is determined by the input of a clock signal and at least one signal which is not the clock signal, is provided which comprises: storing information about the logic circuit in a first storing element; grouping the pairs of the elements into groups based on the clock skew value of the pairs of the elements, wherein each group has a specific range of clock skew values; and computing a delay time for (each of the pairs grouped during the grouping step by using a predetermined clock skew value, which is within the range used during the grouping step, and the information about the logic circuit stored in the first storage element.
According to another aspect of the present invention, a computer-usable storage medium has a computer program which causes a computer to perform the following steps: store information about the logic circuit in a first storing element; group pairs of the elements into groups based on the clock skew value of the pairs of the elements, wherein each group has a specific range of clock skew values; and compute the delay time for each of the pairs grouped during the grouping step, by using a predetermined clock skew value, which is within the range used during the grouping step, and the information about the logic circuit stored in the first storage element.